1. Field of the Invention
This invention relates to frequency synthesizers and more particularly to such a synthesizer which is capable of being programmed or set at a desired frequency to high resolution by means of calculated input controls.
2. Cross Reference to Related Applications
The inventors application (Rational Fraction Synthesizer submitted in Sep. 1991) is incorporated herein by reference.
3. Description of the Prior Art
The frequency synthesizer is a well known and widely used electronic subsystem. Basically, frequency synthesis involves two distinct approaches, sometimes referred to as direct synthesis and indirect synthesis. All such synthesizers utilize a source of reference frequency, such as a quartz oscillator, or atomic standard, or some other highly accurate, fixed frequency reference. The source frequency itself is operated on to provide a wide band of frequencies, each possessing the stability or accuracy of the source. In the direct synthesis approach, the designer may employ dividers, multipliers and such devices which operate on the frequency standard to derive the required output range of frequencies.
In the indirect approach, a VCO or controllable oscillator or other tunable source is used as a generator of the frequency range desired and this is then locked to the source by means of a frequency locked or phase locked loop. Thus one need not utilize complicated filtering schemes as necessary in the direct synthesis approach.
While the frequency synthesizer is characterized above as a separate test instrument, the techniques have found widespread use in the communications field as a local oscillator for a radio receiver or transmitter. A good description of some representative synthesizer techniques appear in books such as Digital PLL Frequency Synthesizers by Ulrich L. Rhode (1983); Frequency Synthesizers; Theory and Design 3.sup.rd Ed. by Vadim Manassewitsch; and Microwave Frequency Synthesizers by Ronald C. Sterling.
A commonly used prior art frequency synthesizer is the conventional divide-by-N phase locked loop design that generates frequencies which are multiples of a reference frequency. More specifically, such a frequency synthesizer consists of a voltage (or current) controlled oscillator (VCO), divide-by-N logic which divides the output frequency of the VCO by N to produce a signal of frequency F.sub.c, and a phase (and or frequency) detector which receives the divided output at one input thereof and the reference frequency signal of frequency F.sub.ref at the other input thereof. The output of the phase detector is supplied back to the frequency control input of the VCO through a loop filter so that the output frequency of the VCO, after being divided by N, is equal to the frequency of the reference signal. By changing the value of N, F.sub.out can be changed in frequency steps equal to F.sub.ref.
The prior art also includes the ability to divide a reference signal by M before it is input to the phase detector at a comparison frequency F.sub.c. This is done because the best frequencies for building good reference clocks (e.g.: 3 to 5 MHz for crystals) are often not the best frequencies for comparison F.sub.c. Thus an M divider is often used to divide down from the best F.sub.ref frequency to the chosen F.sub.c ; but it is fixed at one value--or ocassionally two--, when two different F.sub.c 's are to be provided. Thus even if the prior art apparatus allowed M to be programmed, said programming was done just once, and not updated for each new requested F.sub.req. To improve the frequency resolution of such prior art synthesizers, the designer had to decrease F.sub.c, but many important characteristics such as speed of lock, noise rejection (especially microphonics), F.sub.c rejection, and so on limit the amount by which F.sub.c can be reduced. This same tradeoff exists even in the present invention, but the teaching of this invention makes the tradeoff much less strict.
Other prior art combines a single PLL and a variable timebase. This may take any of several forms. First, a single PLL may be driven by a direct digital synthesizer (DDS) subsystem used as a variable timebase, wherein the PLL becomes a "course" loop, while the DDS forms a "fine" source. The DDS is called on to "fill in the steps" between the "course" steps of the PLL. Such art has become more popular, but it still is expensive and still has inherent noise problems. Another version uses a PLL driven by a variable clock consisting of a crystal oscillator that is "pulled" by a small amount, again to effectively fill in between the "course" steps of the final loop. Though this latter technique is less expensive and does not have the noise problems of the DDS technique, it does have at least three problems of its own: First, the output is now based not on a high quality stable source, but rather on a "pulled" crystal, so overall accuracy and stability are compromised. Second, an "external timebase in" cannot be used, because the "pulled" crystal is not locked to anything. Third, an "internal timebase out" cannot be provided, because none exists; the "pulled" crystal signal is of little value to a user, because it is not constant or at a "standard" frequency. And even if a user just used it relative to the overall synthesizers output, said overall output would then fall back to only having "course" resolution relative to the (variable) timebase out.
Another characteristic of prior art variable clocks, is that they must be designed to have their step size constant, or nearly so, whereby the gaps in between the "course" steps can be filled in evenly. The "steps" of the present inventions adjustable timebase are not required to be even, as will be described below.
Synthesizers that use two PLL's and where the output of one phase locked loop is used as the reference input to another, are known in the art. Such prior art however, does not generally program all four of the division numbers, nor re-program them for each new requested frequency. Nor does this prior art have a calculation means with a calculation procedure for finding the best values for M, N, P, and Q. The present invention uses a rational fraction calculation procedure to improve resolution over this simple prior art.
Other prior art (this inventors patent application entitled "Rational Fraction Synthesizer") uses a rational fraction approximation calculation, and in one of its forms it uses a reference phase locked loop loaded with stored numbers to further enhance the ability of the calculation procedure to arrive at low error values for the second loop. The present invention improves over this prior art by synergistically combining the calculation procedure for the first loop and the calculation procedure for the second loop according to the teaching of the invention. It provides better overall resolution than would be provided by two separate prior art loops, one feeding the other but wherein their calculations were done separately.